A real synthesizer (Yosys, Quartus, Vivado) builds a netlist of generic gates from your Verilog, then maps that to the target FPGA's primitive cells: LUTs (Look-Up Tables, which are tiny ROMs holding any boolean function of K inputs), DFFs, dedicated DSP slices, and block RAM. The cell counts in the side rail come from a fast pattern-matching pass on the AST — not a real netlist — but they're calibrated against the same heuristics the toolchain uses.

The fmax estimate walks every combinational path between flip-flops, counts how many LUT levels deep it is, multiplies by the per-LUT delay for the chosen FPGA family. For an iCE40 that's ~1.5 ns; for a Series-7 it's ~0.4 ns. The slowest path sets the maximum clock.

Inferred latches (incomplete always @(*)) and multiple drivers turn into red warnings — these are the classes of bug that synth tools will compile but you almost never want.